Senior Physical Design Verification Layout Engineer

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel +2

Senior Physical Design Verification Layout Engineer role at NVIDIA, focusing on the design and verification of high-speed communication chips. Responsibilities include chip floorplan, pin placement, physical verification flows, and physical layout implementation. Requires 5+ years of layout experience, strong background in Physical Verification (ERC, LVS, DRC), knowledge of advanced silicon process technologies, and familiarity with EDA tools (Synopsys, Cadence). Experience with Linux, scripting (TCL, Python), data collection, and chip/die verification is a plus. Mentions AI tools orientation as a way to stand out.

What you'd actually do

  1. You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
  2. We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
  3. You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

Skills

Required

  • 5+ years of hands-on layout experience
  • Strong background in Physical Verification methodology (ERC, LVS, DRC)
  • In-depth knowledge of advanced silicon process technologies
  • Familiarity with physical build EDA tools (Synopsys, Cadence)

Nice to have

  • Experience in Linux environments
  • TCL, Python, shell scripting abilities
  • Experience with data collection and analysis
  • Understanding of the chip and die verification process
  • AI tools orientation