Senior Post Silicon Hsio Bringup Lead

NVIDIA NVIDIA · Semiconductors · Bangalore, India +1

NVIDIA is seeking a Senior Post Silicon HSIO Bringup Lead to own the post-silicon validation and support new hardware bring-up for HSIO interfaces (PCIe, CXL, NVLink) on GPU accelerated computing platforms. The role involves test plan development, automation, bug resolution, and influencing pre-silicon methodologies. Requires extensive experience in HSIO protocols, lab instruments, and post-silicon bring-up.

What you'd actually do

  1. Own HSIO (PCIe, CXL, and NVLink) validation on FPGA/Emulator and Silicon, including test plan development, board building for validation requirements, resource planning, automation, test execution, coverage metrics, bug resolution, and release to production.
  2. Coordinate with internal and external logic, circuit, boards, simulation, diagnostics, firmware, driver, and marketing teams across different time zones. Ensure our products are tested against and meet specifications, are tuned for efficient workload performance. Drive the system into production.
  3. Participate in reviewing board schematics, PCB layouts, and making build and component suggestions. Ensure interoperability with connected devices and system components in sophisticated interconnect topologies.
  4. Provide engineering support during manufacturing in both NPI and MP stages of production.
  5. Influence pre-silicon development and verification methodologies, workflows based on issues observed and debugged on silicon to achieve outstanding HSIO products.

Skills

Required

  • BS or B.Tech or MS or M.Tech in EE, ECE, CS, or equivalent degree
  • 7+ years or more experience in HSIO validation
  • Comprehensive understanding of HSIO protocols (PCI Express, Infiniband, Ethernet)
  • Strong knowledge of lab instruments (DSOs, BERT, Protocol/Logic analyzers)
  • Hands-on experience in Post-Si bring-up, functional validation, troubleshooting, and tuning of HSIO interfaces
  • Proficient with logic and protocol analyzers, along with protocol exercisers
  • Outstanding verbal and written communication skills
  • Collaborating across geographically distributed teams and suppliers
  • Proven leadership experience in PCI Express physical layer and debugging LTSSM failures
  • Familiarity with data link layer, transaction layer and CXL
  • Extensive knowledge of characterization techniques in post-silicon settings
  • Excellent knowledge of signal integrity concepts, silicon characteristics, and high-speed/SERDES functional validation
  • Familiarity with x86/Arm server architectures and latest accelerated computing server architecture

Nice to have

  • developing workflows and coding in scripting languages like Python
  • Experience with datacenter products including system management, security, networking, and storage
  • Working exposure on working with AI tools (like Claude or Cursor)

What the JD emphasized

  • 7+ years or more experience in HSIO validation
  • Comprehensive understanding of the HSIO protocols (including PCI Express, Infiniband, Ethernet), its specifications, and its operation at a system level.
  • Strong knowledge of lab instruments (DSOs, BERT, Protocol/Logic analyzers) and hands-on experience in Post-Si bring-up, functional validation, troubleshooting, and tuning of HSIO interfaces. Proficient with logic and protocol analyzers, along with protocol exercisers.
  • Proven leadership experience in PCI Express physical layer and debugging LTSSM failures; familiarity with data link layer, transaction layer and CXL.
  • Extensive knowledge of characterization techniques in post-silicon settings. Excellent knowledge of signal integrity concepts, silicon characteristics, and high-speed/SERDES functional validation.
  • Familiarity with x86/Arm server architectures and latest accelerated computing server architecture is required.