Senior Power and Performance Engineer - System Memory

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Senior Power and Performance Engineer to focus on system memory features. The role involves building roadmaps, architecting, designing, and integrating memory system-level features to optimize performance, power, and reliability. Responsibilities include collaborating with cross-functional teams, leading debug efforts, and staying updated on industry trends. The ideal candidate will have a strong background in memory subsystem architecture, design, validation, and hands-on lab experience.

What you'd actually do

  1. Build roadmaps of memory system-level features to address low power, low noise, perf/watt efficient, and stable/reliable product needs by doing prototyping, use case analysis, and system-level cost/benefit tradeoff.
  2. Architect, design, and integrate memory system-level features, controllers, and policies - including binning, pairing, and adaptive control techniques based on the roadmap to optimize product performance, power, and reliability/stability.
  3. Collaborate with architecture, ASIC, board/platform design, software/firmware, marketing, and other multi-functional teams to drive architecture, design, and debug.
  4. Expand power improvement initiatives to cover various products and market segments, including high-demand environments such as data centers. Drive scalable, power-efficient, and reliable memory system solutions across diverse platforms.
  5. Lead debug, craft WARs, and support bringup, validation, manufacturing, and customer issues on relevant features.

Skills

Required

  • BS or MS degree in EE/CE or equivalent experience.
  • 8+ years of experience in memory subsystem architecture, design, and validation, with a strong focus on system-level features that optimize memory power for perf-per-watt efficiency in datacenter or high-perf systems.
  • Strong fundamentals in EE, digital/analog design, signal integrity, low power design, memory power management techniques, timing analysis, and architecture.
  • Experience with control systems, boot/reset flows, and memory controller micro-architecture.

Nice to have

  • Experience with Python, Perl, C/C++, Windows, and Linux is a plus.

What the JD emphasized

  • Prior experience in the lab with system-level post-silicon bring-up and debug is highly desired.
  • It is crucial to have a deep understanding of how system-level memory interacts with different IPs and SW/FW, including their impact on power, latency, and reliability.
  • Validated hands-on lab experience with silicon bringup, lab debug, and lab tools (oscilloscopes, multimeters, logic analyzers).