Senior Power Integrity Methodology Cad Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

Senior Power Integrity Methodology CAD Engineer at NVIDIA, focusing on developing and implementing physical design methodologies for rail analysis and signoff for NVIDIA chips. Requires expertise in EMIR flow, scripting, and collaboration with hardware/design teams.

What you'd actually do

  1. Developing physical design methodologies for rail analysis and signoff.
  2. Responsible for coming up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
  3. Crafting workflows and tool methodologies for power and noise analysis across multiple projects.

Skills

Required

  • Electrical Engineering or related field
  • EMIR flow methodology development and support
  • EMIR analysis and signoff
  • hierarchical design approach and hierarchical signoff
  • shift-left methodologies for EMIR optimization
  • TCL
  • Perl
  • Python
  • C++

Nice to have

  • crafting custom workflows from scratch
  • AI tools to improve capabilities in the power integrity domain

What the JD emphasized

  • Minimum 5+ years of experience in EMIR flow methodology development and support
  • Strong understanding of all aspects of EMIR analysis and signoff
  • Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle