Senior Pre-silicon Soc Modeling Engineer, Annapurna Labs Machine Learning Accelerators, Aws

Amazon Amazon · Big Tech · Cupertino, CA · Software Development

Senior Pre-Silicon SoC Modeling Engineer for AWS Machine Learning Accelerators. The role involves building and owning C++ models of custom SoCs (Trainium and Inferentia) used by RTL designers, verification engineers, and software teams. Responsibilities include translating architecture specs into models, validating against RTL, developing model-based test infrastructure, and contributing to performance modeling. The role emphasizes ownership and impact on silicon development, with a clear path into architectural modeling. No ML background is required as the domain knowledge will be learned on the job.

What you'd actually do

  1. Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
  2. Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
  3. Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
  4. Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
  5. Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams

Skills

Required

  • 6+ years of full software development life cycle
  • Experience as a mentor, tech lead or leading an engineering team
  • 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
  • Experience programming in C++, using advanced language features
  • Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Nice to have

  • Experience working with DV teams or integrating models into verification flows
  • Experience correlating functional models against RTL simulation, emulation, or silicon
  • Experience developing and calibrating performance models for custom silicon
  • Experience with SystemC, TLM, or cycle-approximate modeling methodologies
  • Experience building regression and CI frameworks for model validation
  • Familiarity with Modern C++ (20 and beyond)
  • Experience with multi-threaded or distributed simulation
  • ML accelerator architecture knowledge

What the JD emphasized

  • save months of schedule and millions of dollars
  • deep visibility into how custom ML accelerators are architected
  • own significant pieces of the stack
  • 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
  • Experience programming in C++, using advanced language features
  • Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture