Senior Pre-silicon Verification Engineer

Intel Intel · Semiconductors · Toronto, ON

Senior Pre-Silicon Verification Engineer specializing in mixed-signal verification for semiconductor designs. Responsibilities include developing verification strategies, creating behavioral models, executing verification plans, and debugging pre-silicon environments.

What you'd actually do

  1. Perform functional verification of digital and mixed-signal logic components including analog behavioral modeling and advanced verification techniques (UVM, real number modeling, AMS simulation).
  2. Create verification environments that accurately model analog-digital interactions and validate designs across process, voltage, and temperature (PVT) variations.
  3. Develop comprehensive IP verification plans, test benches, and scalable verification environments for mixed-signal microarchitecture specifications.
  4. Build verification frameworks supporting regression testing, continuous integration, and both digital and analog verification flows.
  5. Execute verification plans, analyze power/timing/performance metrics, and conduct system-level simulations and corner case analysis.

Skills

Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related field of study
  • 5+ years of experience in digital design verification or mixed-signal verification
  • 3+ years of experience with Pre-Silicon Verification environment architecture and development
  • Experience with complex mixed-signal IP verification or system-level verification
  • Experience in both digital verification methodologies (UVM/SystemVerilog)
  • Perl, HTML, Python or similar scripting (Python preferred)

Nice to have

  • Master's degree in Electrical Engineering, Computer Engineering, or in a STEM related field of study
  • Experience with working in mixed-signal design like SerDes or PLLs
  • Experience with SerDes PHY verification
  • Experience driving verification methodology changes and initiatives
  • Experience with Mixed Signal Verification (MSV)
  • Experience with Gate Level Simulation (GLS)
  • Experience with concepts of DFT, ATE, HVM

What the JD emphasized

  • 5+ years of experience in digital design verification or mixed-signal verification
  • 3+ years of experience with Pre-Silicon Verification environment architecture and development
  • Experience with complex mixed-signal IP verification or system-level verification
  • Experience in both digital verification methodologies (UVM/SystemVerilog)