Senior Product Development Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on product development engineering for NVIDIA's GPUs, driving latest architecture designs to market, enhancing manufacturing efficiency, and resolving yield and test failures. It involves cross-functional collaboration with design, foundry, and test teams to root-cause technical problems and influence future ASIC designs for improved yield and testability. The role requires a Master's degree in Electrical Engineering or equivalent experience, 8+ years of experience, and proficiency in digital design, circuit analysis, characterization, qualification, and statistical data analysis.

What you'd actually do

  1. As an integral part of product engineering, you will drive our latest architecture designs to market.
  2. Design FT (final test) test processes to enhance manufacturing efficiency for our latest GPUs, built in leading-edge process technology.
  3. Identify and resolve yield bottlenecks, analyze and drive test failures, wafer & package level failures on Automatic Test Equipment (ATE).
  4. Propose DOEs and come up with solutions to complex characterization problems.
  5. Cross functionally lead efforts with design, foundry, DFT, test, Planning and quality to root-cause and solve technical problems.

Skills

Required

  • Master's degree in Electrical Engineering or equivalent experience
  • 8+ years of product development engineering or relevant experience
  • Attention to details
  • strong problem solving skills
  • data driven decisions
  • critical thinking & solution focused
  • Experience with digital design, circuit analysis, characterization and qualification
  • Knowledgeable in ATE test flows, DFT and device physics
  • Proficient in statistical data analysis using JMP software or other tools
  • Strong interpersonal communication skills
  • cross-functional collaboration
  • Ability to define and drive problems to closure independently with minimal supervision

Nice to have

  • Hands-on skills with Advantest 93K tester with SMT7 or SMT8 OS
  • Knowledge of test time and DPPM reduction
  • Experience with logic or SRAM and Voltage/Frequency characterization
  • With DFT (design for test) background and be familiar with ATE test principles
  • Examples of creative solutions to silicon or package problems
  • scripting/programming knowledge (Python or Perl)

What the JD emphasized

  • drive our latest architecture designs to market
  • resolve yield bottlenecks
  • analyze and drive test failures
  • root-cause and solve technical problems
  • influence future ASIC designs