Senior Reliability Engineer - Lpu Packaging

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior Reliability Engineer for LPU packaging at NVIDIA, focusing on package-level reliability specifications, qualification, materials selection, and data analysis for IC packaging and board-level reliability.

What you'd actually do

  1. Own the package‑level reliability spec for assigned products
  2. Define qualification requirements and pass/fail criteria for device/package‑level reliability (e.g., HTSL, TCT, UHAST, pre‑conditioning, JESD22 methods) and Package‑on‑board / board‑level reliability (thermal cycling, shock/vibration, connector/cage interactions)
  3. Leads materials and stackup selection (substrate, solder alloy, underfill, mold, lid, TIM, etc.) and DFR trade‑offs for new packages and 2nd sources
  4. Evaluates thermo‑mechanical and SI/PI impact of those choices
  5. Analyzes qual and stress data (including HTOL, package qual, SLT/system stress) and convert to design / process/ material changes for next revision.

Skills

Required

  • MS/PhD in Electrical Engineering, Materials Science, Mechanical Engineering, or related field, or equivalent experience.
  • 8+ years of relevant experience
  • IC packaging
  • Board level reliability
  • BGA/FCBGA
  • 2.5D/3D integration
  • HBM
  • JEDEC device/package reliability standards
  • HTSL
  • TCT
  • UHAST
  • pre-conditioning
  • board level solder reliability
  • system-level stress
  • SLT
  • interpreting logs/telemetry for reliability analysis
  • FIT
  • MTTF/MTBF
  • AFR
  • RAS concepts

Nice to have

  • lead cross-functional efforts
  • data center or cloud hardware
  • Rack and cluster-level availability targets and constraints
  • component FIT drive sparing, repair rate, and availability planning
  • Strong communication
  • present trade-offs and reliability risks clearly

What the JD emphasized

  • 8+ years of relevant expiernce
  • Strong background in IC packaging and board level reliability, with hands on experience in:
  • Experience with BGA/FCBGA, 2.5D/3D integration, HBM or similar high power, high pin count packages
  • Background with JEDEC device/package reliability standards (e.g., HTSL, TCT, UHAST, pre con, board level solder reliability)
  • Knowledge in system‑level stress or SLT and interpreting logs/telemetry for reliability analysis.