Senior Rtl Design Engineer

Intel Intel · Semiconductors · Texas, Austin, United States +1

Senior RTL Design Engineer role focused on developing Intel's next-generation microprocessors. Responsibilities include defining, designing, and implementing CPU architecture and microarchitecture features, developing logic design and RTL coding, optimizing designs for power, performance, area, and timing, and collaborating with cross-functional teams. Requires expertise in RTL design using Verilog/System Verilog, low-power design methods, and scripting languages.

What you'd actually do

  1. Collaborate on the definition, design, and implementation of CPU architecture and microarchitecture features.
  2. Develop logic design, register transfer level (RTL) coding, and simulation for CPU components, including cell libraries, functional units, and CPU IP blocks for full-chip integration.
  3. Optimize logic designs to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation.
  4. Review verification plans and implementations, resolving issues and applying corrective measures to ensure feature correctness in RTL tests.
  5. Document microarchitectural specifications (MAS) for the CPU features you design.

Skills

Required

  • Bachelor's degree in Electrical/Computer Engineering, Computer Science or related filed with 9+ years of relevant experience. Or a Master's degree in the same field with 7+ years of experience.
  • 7+ years of experience in RTL design using Verilog, or System Verilog, with strong knowledge of hardware modeling and logic debug environments.
  • 7+ years of experience in Modern energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
  • 4+ years of experience in cross-clock domain crossings and power aware design.
  • 4+ years of experience in scripting languages such as TCL, Perl, or Python.

Nice to have

  • Knowledge on CPU power-management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
  • Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
  • Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
  • Familiarity with circuit planning and timing convergence processes.
  • Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
  • Proficient with static timing analysis, UPF and lint checks.

What the JD emphasized

  • 9+ years of relevant experience
  • 7+ years of experience in RTL design using Verilog, or System Verilog
  • 7+ years of experience in Modern energy-efficient and low-power logic design methods
  • 4+ years of experience in cross-clock domain crossings and power aware design
  • 4+ years of experience in scripting languages such as TCL, Perl, or Python