Senior Rtl Design Engineer, Machine Learning Accelerators

Google Google · Big Tech · Sunnyvale, CA +1

Senior RTL Design Engineer focused on AI/ML hardware acceleration for Google's TPUs. Responsibilities include designing and verifying complex digital ASIC blocks, collaborating with software teams, and improving overall chip design for AI/ML applications.

What you'd actually do

  1. Understand the overall application of the chip, proposing and developing improvements in overall design.
  2. Design and document one or more blocks of an ASIC, including functionality and timing.
  3. Work closely with software teams on functionality, interfaces, and documentation.

Skills

Required

  • custom silicon design
  • RTL design
  • Verilog
  • SystemVerilog
  • Electrical Engineering
  • Computer Engineering
  • Computer Science

Nice to have

  • computer architecture
  • software
  • architecture
  • scripting language
  • Python
  • Perl
  • code review
  • testing
  • refactoring
  • high-performance design
  • low power design
  • processor design
  • accelerators
  • memory hierarchies