Senior Signal and Power Integrity Engineer

NVIDIA NVIDIA · Semiconductors · Taipei, Taiwan +1

NVIDIA is seeking a Senior Signal and Power Integrity Engineer to work on chip package and PCB design analysis for high-speed mixed-signal circuit design challenges. The role involves system-level power integrity simulations, PDN design and optimization, SI channel analysis, simulation automation, and post-layout SI/PI model extraction.

What you'd actually do

  1. Work on crafting creative Signal and Power Integrity solutions to complex system design problems
  2. System-level power integrity simulations of NVlinks 200Gbs+, PCIe, and other HSIO such as DP2.1/HDMI2.1/CSI/USB4.
  3. Design and optimize Power Delivery Network (PDN) across interposers, packages, and PCBs.
  4. SI channel analysis for spec development: DP2.1/HDMI FRL2. Constant improvements of SI/PI models through lab measurements
  5. Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.

Skills

Required

  • BS/MS-Electrical Engineering or equivalent experience
  • 5+ years of industry experience
  • Strong understanding of electromagnetics including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge.
  • Hands on use of 3/2.5-D modeling tools like ANSYS HFSS/Q3D/SIwave, Cadence PowerSI.
  • Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations for power noise.
  • Experience with die power delivery modeling – mixed-signal blocks & digital and associated tools like CSM/Redhawk, Raptor-X.
  • Familiarity with voltage regulator modeling for board power supplies using simplis or spice. Familiarity with use of VNA, TDR, DSO.
  • Familiarity with transient simulation in tools and understanding of eye diagram methodology.
  • Have measurement and simulation correlation experience.

Nice to have

  • Matlab, Python, VBS, or C for simulation automation
  • Exposure to interface timing budgets and system modeling
  • SI analysis flow including frequency and time domain simulation
  • PDN analysis flow including model generation and time domain simulation
  • PSIJ Analyses involving co-simulation of circuits and PDN models
  • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes
  • Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts
  • Understanding of high-volume manufacturing variations and impact to channel signal integrity

What the JD emphasized

  • 5+ years of industry experience
  • Strong understanding of electromagnetics including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge.
  • Hands on use of 3/2.5-D modeling tools like ANSYS HFSS/Q3D/SIwave, Cadence PowerSI.
  • Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations for power noise.
  • Experience with die power delivery modeling – mixed-signal blocks & digital and associated tools like CSM/Redhawk, Raptor-X.
  • Familiarity with voltage regulator modeling for board power supplies using simplis or spice. Familiarity with use of VNA, TDR, DSO.
  • Familiarity with transient simulation in tools and understanding of eye diagram methodology.
  • Have measurement and simulation correlation experience.