Senior Silicon Digital Design Engineer, Core Ip

Google Google · Big Tech · Bengaluru, Karnataka, India

Develop custom silicon solutions for Google's direct-to-consumer products, focusing on microarchitecture definition, RTL implementation, and ASIC design methodologies. This role is within the Platforms and Devices team, which works on computing software platforms and first-party devices, aiming to make user interactions faster and more seamless.

What you'd actually do

  1. Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration.
  2. Define and develop RTL implementations that meet power, performance and area goals.
  3. Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  4. Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
  5. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.

Skills

Required

  • digital logic design principles
  • RTL design concepts
  • Verilog
  • SystemVerilog
  • logic synthesis techniques
  • low-power design techniques
  • ASIC design methodologies
  • clock domain checks
  • reset checks

Nice to have

  • machine learning accelerators
  • camera ISP image processing IP
  • multimedia IPs
  • scripting languages
  • C/C++ programming
  • software design skills
  • high-performance design techniques
  • assertion-based formal verification
  • FPGA
  • emulation platforms
  • SOC architecture

What the JD emphasized

  • 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
  • Experience with ASIC design methodologies for clock domain checks and reset checks.