Senior Silicon Product Engineer, Dfp – Manufacturing

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

This role focuses on defining and implementing validation and screening of new silicon features in high-volume manufacturing. The engineer will translate product requirements into test methodologies, infrastructure, and detailed manufacturing test plans to ensure quality, yield, and throughput. The role involves cross-functional collaboration to integrate testability into the design lifecycle and define data/analytics frameworks for yield analysis and continuous improvement. Experience in silicon post-silicon validation and high-volume manufacturing test for complex SoCs is required, along with proficiency in scripting and data analysis. While AI tools are mentioned for accelerating analysis and documentation, the core function is not AI model development but rather manufacturing test engineering for silicon products.

What you'd actually do

  1. Own end-to-end manufacturing test methodology across all test stages.
  2. Translate system specs and product POR into DFP requirements, test content, coverage, and flows.
  3. Define and maintain the DFP roadmap, including infrastructure and milestone planning.
  4. Partner cross-functionally to implement test content, debug hooks, and coverage improvements.
  5. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs.

Skills

Required

  • MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience)
  • 6+ years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar.
  • Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization.
  • Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data mining, limit tuning, and yield/debug analysis.
  • Demonstrated ability to drive cross‑functional alignment around plans, dependencies, and sign‑off criteria.
  • Excellent communication skills and comfort authoring structured technical documents and test plans used by global manufacturing and validation teams.
  • Strong AI‑enabled skills and thinking - Use AI to accelerate analysis, exploration, and documentation, but also maintain rigor, originality, and judgment that do not come from AI.
  • Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production.

Nice to have

  • Integrate AI tools (LLMs, copilots, intelligent search) into daily workflows to explore architectures, test strategies, and design options.
  • Use AI to accelerate documentation, DFP development, and creation of scripts and data-analysis tools for optimized coverage and HVM enablement.
  • Apply strong engineering judgment—know when to trust AI outputs, verify against specs/data, or override them.
  • Build AI-assisted validation and debug workflows (e.g., log triage, anomaly detection, pattern recognition, data analysis).
  • Share AI-driven best practices, prompts, and tools to elevate team productivity while maintaining technical rigor.

What the JD emphasized

  • Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production.