Senior Soc Debug Verification Engineer

Microsoft Microsoft · Big Tech · Bengaluru, KA, IN +2 · Silicon Engineering

This role is for a Senior SOC Debug Verification Engineer at Microsoft, focusing on the design and verification of computer chips for cloud infrastructure. The engineer will be responsible for developing verification strategies, environments, and methodologies, debugging failures, and collaborating with cross-functional teams. The role involves working with hardware manufacturing and ensuring the quality and efficiency of cloud hardware. While the role mentions applying generative AI solutions to verification work, its core function is hardware verification, not AI model development.

What you'd actually do

  1. Own verification of Design for Debug (DFD) SoC level flows including Task planning and schedule estimation, proactively identifying and removing roadblocks and finding ways to make the team more efficient
  2. Develop verification strategy, requirements, environments, tools, and methodologies
  3. Become an expert on the overall debug architecture, understand customer use models, and understand interactions with other parts of the SOC, with the platform, and with software
  4. Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test benches, checkers, coverage, and other verification collateral
  5. Run tests, debug failures to root cause, and recommend fixes

Skills

Required

  • pre-silicon SOC or subsystem or IP verification experience
  • CPU/SOC designs verification experience
  • design for debug verification experience
  • electrical, Electronics, Computer Engineering, Computer Science or a related degree

Nice to have

  • SOC DFD verification for a full product cycle
  • writing SOC level test plans
  • developing tests
  • debugging failures
  • coverage signoff
  • JTAG interface
  • hardware triggers
  • breakpoints
  • tracing
  • ARM Core Sight debug
  • debug features in post-silicon
  • Agile software practices

What the JD emphasized

  • 8+ years of pre-silicon SOC or subsystem or IP verification experience
  • 6+ years of verification experience working on CPU/SOC designs, with 2+ years of design for debug verification experience