Senior Soc Verification Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Senior engineer to build, develop, and maintain scalable verification infrastructure for SoC verification across various environments (Simulation, Emulation, FPGA prototyping, C-model). Focus on ensuring correctness, performance, and quality of NVIDIA's SoCs for AI Datacenters, self-driving cars, robotics, and embedded platforms.

What you'd actually do

  1. Build and develop testbench infrastructure and associated flows for full chip level verification of NVIDIA SoCs
  2. Develop, combine, and support Verification IP (VIP) and reusable verification components
  3. Develop and improve stimulus frameworks supporting: RTL simulation, Hardware emulation, FGPA prototyping, C-model and hybrid model verification.
  4. Work closely with EDA vendors to co-develop and deploy new verification tooling.
  5. Collaborate closely with design, architecture, performance, and software teams to align verification infrastructure with evolving product requirements

Skills

Required

  • SystemVerilog
  • UVM
  • modern verification methodologies
  • testbenches
  • VIP
  • reusable verification frameworks
  • RTL simulation
  • Hardware emulation
  • FPGA prototyping
  • C-model verification
  • virtual platform verification
  • Python
  • Perl
  • automation
  • tooling
  • debugging skills across hardware and software boundaries

Nice to have

  • Electrical Engineering
  • Computer Engineering
  • Computer Science

What the JD emphasized

  • Foundational to ensuring correctness, performance, and quality of NVIDIA’s SoCs used across AI Datacenters, self-driving cars, robotics, and embedded platforms
  • 8+ years in the following areas: SystemVerilog, UVM, and modern verification methodologies
  • Hands-on experience with RTL simulation and at least one of the following: Hardware emulation, FGPA prototyping, C-model or virtual platform verification.