Senior Software Engineer, Cutlass Platform

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +4

Develop core components of the CUTLASS platform including Tensor Core MMAs, copies, synchronization barriers, schedulers, and other GPU hardware features in CUDA C++ and CUTLASS Python DSL. Contribute to the advancement of the MLIR-based backend compiler stack for the CUTLASS Python DSL by designing dialects and associated compiler passes. Author example kernels utilizing CUTLASS abstractions to showcase the use of novel GPU hardware features that are crucial for achieving high performance. Collaborate with GPU architecture, CUDA, and NVVM/PTX compiler teams to provide feedback on programming models and to assess the performance of future GPU hardware features.

What you'd actually do

  1. Develop core components of the CUTLASS platform including Tensor Core MMAs, copies, synchronization barriers, schedulers, and other GPU hardware features in CUDA C++ and CUTLASS Python DSL.
  2. Contribute to the advancement of the MLIR-based backend compiler stack for the CUTLASS Python DSL by designing dialects and associated compiler passes.
  3. Author example kernels utilizing CUTLASS abstractions to showcase the use of novel GPU hardware features that are crucial for achieving high performance.
  4. Collaborate with GPU architecture, CUDA, and NVVM/PTX compiler teams to provide feedback on programming models and to assess the performance of future GPU hardware features.

Skills

Required

  • Masters or PhD degree in Computer Science, Computer Engineering, or related field (or equivalent experience).
  • 3+ years of relevant industry experience.
  • Strong proficiency in C++ programming and software design, including debugging, performance evaluation, and testing.
  • Experience working with high-performance code generation and knowledge of compiler transformations and optimizations.
  • A deep understanding of computer architecture and parallel computing programming models.

Nice to have

  • Experience writing high-performance kernels at low levels of abstractions like NVVM/ PTX for GPUs or other similar parallel processing architectures.
  • Hands-on compiler design experience, particularly in MLIR.
  • Understanding of deep learning models, algorithms, and frameworks.

What the JD emphasized

  • high-performance linear algebra
  • Tensor Core primitives
  • high performance kernels
  • GPU hardware features
  • MLIR-based backend compiler stack
  • novel GPU hardware features
  • high performance