Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
In this role, you will develop C++ code that controls and monitors Google’s custom accelerators (ASICs) - including TPUs for machine learning and video coding unit (VCUs) for video encode/decode. You define the API that the rest of the software stack uses to build deployments of the systems that use these ASICs. You will write code that directly manages interrupts, Direct Memory Access (DMAs), and many other hardware-centric features. You will debug and bring up new ASICs. Our team owns simulation models that allow for early software development pre-silicon. You will work closely with external vendors and many internal teams including chip design, system software, ML supercomputer, compiler, and system test.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Design and build firmware running on embedded micro-controllers with limited memory footprints on the accelerator Application-Specific Integrated Circuits (ASIC).
- Co-design hardware/software interface, and work with the hardware design and development teams.
- Design and develop tools to update and debug ASIC firmware, and enable chip bring-up and hardware debugging.
- Build functional or cycle-level simulators that bit-accurately model the custom accelerator ASICs, build tools and infrastructure to help ASIC design verification, tapeout, and bring-up, and develop embedded CPU simulators as part of the full system simulator.
- Architect and design debuggability mechanisms and telemetry collection systems to monitor Tensor Processing Units (TPUs), enhancing customer satisfaction and enabling rapid response, diagnosis, and mitigation of production failures.
Qualifications
Minimum qualifications:
- Bachelor’s degree or equivalent practical experience.
- 5 years of experience with software development in one or more programming languages.
- 3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture.
- 3 years of experience working with embedded operating systems.
Preferred qualifications:
- Master's degree in Computer Science or a related technical field, or equivalent practical experience.
- Experience with Embedded software development in C/C++.
- Experience with machine learning (ML), security, and confidential computing, as well as high bandwidth memory (HBM), peripheral component interconnect express (PCIe), and advanced RISC machines (ARM).
- Experience with hardware/software co-design at the chip-level.
- Experience with architecting scalable software, multi-threaded designs, and implementation.