Senior Software R&d Engineer, Digital Logic Synthesis

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

NVIDIA is seeking an EDA Software R&D Engineer to develop internal EDA tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++. The role involves inventing and developing new algorithms for RTL synthesis, digital logic optimization, and physical-aware synthesis techniques, with a focus on prototyping and evaluating ML methods to guide optimization decisions and integrating successful approaches into production.

What you'd actually do

  1. Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
  2. Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
  3. Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
  4. Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
  5. Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.

Skills

Required

  • MS or PhD in Electrical Engineering or Computer Science or equivalent experience
  • 6+ years experience in EDA software and/or VLSI flows, with significant work in logic synthesis or digital optimization.
  • Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing).
  • Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
  • Expertise in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers
  • Good communication and interpersonal skills

Nice to have

  • Previous work experience involving RTL logic synthesis and multi stage logic optimization
  • Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization
  • Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
  • Experience with various machine learning techniques.

What the JD emphasized

  • ML methods (e.g., GNNs, RL, models) to guide optimization decisions
  • prototype and evaluate ML methods
  • integrate successful approaches into production

Other signals

  • ML methods (e.g., GNNs, RL, models) to guide optimization decisions
  • prototype and evaluate ML methods
  • integrate successful approaches into production