Senior Sram Circuit Design Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and explore future process nodes. Responsibilities include transistor-level circuit design, supervising layout, verification, debug, and automating the assembly and validation of SRAM macros. The role also involves collaborating with SOC design, silicon test, and productization teams.

What you'd actually do

  1. Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
  2. SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
  3. Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.
  4. Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.

Skills

Required

  • BSEE minimum (or equivalent experience)
  • 3+ years of SRAM design experience
  • strong background in digital circuit design, layout, and validation on advanced FinFET processes
  • Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers
  • Python scripting ability to parse data and automate tasks
  • Successful track record of delivering designs to production

Nice to have

  • MSEE or PhD preferred
  • Self-motivation, attention to detail, and good written, verbal, and presentation skills
  • A high degree of scripting expertise in Python
  • Familiarity with Cadence schematic and layout capture tools
  • Silicon testing/debug experience

What the JD emphasized

  • Successful track record of delivering designs to production