Senior Sta Engineer, Sub-chip

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel +1

NVIDIA is seeking a Senior STA Engineer to perform advanced Static Timing Analysis (STA) at chiplet and FC level, run Prime Time, debug timing paths, and ensure convergence throughout various project stages. The role requires B.SC./M.SC. in Electrical Engineering and 5+ years of hands-on STA experience.

What you'd actually do

  1. Perform advanced Static Timing Analysis (STA) at chiplet and FC level.
  2. Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
  3. Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
  4. Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

Skills

Required

  • B.SC./ M.SC. in Electrical Engineering
  • 5+ years of hands-on STA experience
  • Experience in Prime Time and signoff methodologies
  • Excellent leadership capabilities

Nice to have

  • Knowledge in physical design flows and methodologies (Synthesis, PNR, DFT designs)
  • Trong background of Prime time tool
  • Great teammate

What the JD emphasized

  • full timing closer and quality approval from pre-layout STA model through signoff