Senior Staff Analog Circuit Design Engineer - Serdes

Intel Intel · Semiconductors · Toronto, ON

Senior Staff Analog Design Engineer focused on high-speed SerDes applications (112G and 224G) for data centers, AI infrastructure, and communication networks. Responsibilities include designing analog blocks, collaborating with cross-functional teams, leading validation and optimization, and mentoring junior engineers. Requires Master's degree, 5+ years of analog/mixed-signal design experience, and expertise in specific analog domains and simulation tools. Preferred qualifications include a Ph.D., more experience, and knowledge of next-gen standards and system-level modeling.

What you'd actually do

  1. Design high-performance analog blocks and subsystems that define industry standards
  2. Work alongside world-class system architects, digital designers, and layout engineers
  3. Drive post-silicon validation and performance optimization initiatives
  4. Shape the next generation of analog designers while providing technical leadership
  5. Tackle complex challenges in high-speed communication systems with creative solutions

Skills

Required

  • Master's degree in electrical/Electronic Engineering or related field
  • 5+ years of proven experience in analog/mixed-signal circuit design for high-speed SerDes
  • Experience in one or more domains: PLL, CDR, CTLE, DFE, ADC, or Transmitter design
  • Standards knowledge: PCIe (Gen4/Gen5) and Ethernet (100G/400G) experience
  • Technical mastery: Core analog design principles (noise, linearity, matching, stability)
  • Process expertise: Hands-on experience with advanced FinFET CMOS technologies
  • Tool proficiency: Cadence Virtuoso/ADE, HSPICE, or equivalent simulation platforms
  • Lab experience: Silicon validation, measurements, and analog circuit debugging

Nice to have

  • Ph.D. in Electrical/Electronic Engineering
  • 7+ years of specialized SerDes analog design experience
  • Advanced knowledge: Transmitter/receiver design, CDR loops, equalization techniques
  • Next-gen standards: PCIe 6.0, 800G Ethernet, JESD exposure
  • Modeling expertise: Verilog-A, MATLAB simulations, automation scripting (Python, Tcl)
  • System understanding: Signal integrity, channel modeling, link analysis
  • Leadership qualities: Cross-functional collaboration and technical review contributions