Senior/staff Engineer : Post Silicon- Bring up

Cerebras Cerebras · Semiconductors · Headquarters +2 · Silicon

This role focuses on the post-silicon bring-up and optimization of Cerebras's Wafer Scale Engine (WSE), a large AI chip. The engineer will develop and debug production processes, refine AI systems across hardware/software constraints, enhance infrastructure for workload testing, and work with cross-functional teams to optimize performance. The role involves significant hardware and software co-design, testing, and automation.

What you'd actually do

  1. On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs
  2. Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
  3. Develop/Enhance infrastructure to enable silicon for real world workload testing
  4. Develop self-checking metrics, as well as instrumentation for debug and coverage
  5. Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.

Skills

Required

  • BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
  • 7-10+ years of industry experience
  • 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
  • Good understanding of computer architecture and networking
  • Excellent Coding in languages such as Python/Verilog/System Verilog and C
  • Proficient in hardware/software codesign and layered architectures.
  • Excellent debugging, analytical, and problem-solving skills
  • Proficient in large scale testing and automation using pytest and python
  • Good presentation skills to refine diverse information and put forth optimization strategies and results.
  • Good interpersonal skills, ability & desire to work as a standout colleague
  • Proven track record of working cross-functionally learning fast and driving issues to closure

Nice to have

  • Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
  • Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
  • Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
  • Familiarity in creating test and s/w infrastructure at large scale
  • Working across global time zones

What the JD emphasized

  • Pre-silicon & Post Silicon ASIC hardware
  • hardware/software codesign
  • large scale testing and automation