Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will define how Google verifies the world's fastest interconnects. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that the "Golden Models" we use in design actually match the behavior of the silicon in our AI data centers.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define the global verification methodology for the Google Cloud Silicon Digital Signal Processing (DSP) group, driving the adoption of advanced techniques like Formal Verification, Portable Stimulus Standard (PSS), or Machine Learning (ML)-driven stimulus generation.
- Lead the transition of DSP verification from simulation to Hardware Emulation (Palladium/Zebu) to enable long-latency testing and stress tests that are impossible in standard Register Transfer Level (RTL) simulators.
- Architect the bridge between pre-silicon verification and post-silicon validation. Define the telemetry and monitors required in the silicon to correlate lab measurements back to the Design Verification (DV) models.
- Establish the rigorous sign-off criteria for tape-outs, balancing verification depth against project schedules.
- Drive verification standards for next-generation interconnects, ensuring our internal tools and vendor road maps align with future silicon needs.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
- 12 years of experience in Design Verification with a focus on Mixed-Signal or Physical Layer (PHY) interfaces.
- Experience with Hardware Emulation, FPGA Prototyping, or DSP validation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience managing Industry Standards or methodologies in Verification (e.g., Portable Stimulus, ML-driven DV).
- Experience defining Verification Roadmaps for transistor SoCs or high-bandwidth networking chips.
- Experience integrating Pre-Silicon Verification and Post-Silicon Validation.
- Experience with Total Cost of Verification (TCV) (e.g., balancing simulation time, emulation capacity, and schedule risk).