Senior System Validation Methodology Engineer

NVIDIA NVIDIA · Semiconductors · Shanghai, China

NVIDIA is looking for a Senior System Validation Methodology Engineer to develop and lead silicon validation methodologies, debug complex system-level issues, and drive automation. The role involves working with HW and SW teams, bringing up new flows on pre-silicon platforms, and applying AI to semiconductor co-design and validation problems.

What you'd actually do

  1. Develop new end-to-end methodologies, processes, and workflows targeting system-level silicon stress, concurrency, and PVT coverage.
  2. Lead debug efforts from the HW side to root cause feature sequences bugs, silicon bugs, and sophisticated system-level issues caused by interactions between multiple HW and SW features.
  3. Drive SW team on system validation test development, automation and efficiency improvement.
  4. Bringup new flows, tests, and PVT solutions at Pre-si on N-1 or Emulation/FPGA platform.
  5. Apply insights from bring-up execution and post-action reviews to continually improve coverage.

Skills

Required

  • BS or MS degree in EE/CE or equivalent experience
  • 5+ years of experience in silicon validation and stress testing, PVT methodologies
  • Deep understanding of GPU/SOC system-level architecture
  • Experience with silicon active and low power features, boot, binning, PVT sensitivity, platform component losses
  • Post silicon debug and evaluate fix options
  • Effective collaboration and communication across different functional teams

Nice to have

  • Experience in applying AI to semiconductor co-design/validation problems
  • Knowledgeable in using AI-assisted workflows to accelerate automation, data analysis, root cause investigation, and documentation.

What the JD emphasized

  • 5+ years of experience in some of the following areas:
  • Developing end-to-end silicon validation and stress testing, PVT methodologies for next-generation silicon
  • Deep understanding of GPU/SOC system-level architecture
  • Working experience with silicon active and low power features, boot, binning, PVT sensitivity, platform component losses
  • Post silicon debug and evaluate fix options against product needs.
  • Experience in applying AI to semiconductor co-design/validation problems and learning the domain quickly.
  • Knowledgeable in using AI-assisted workflows to accelerate automation, data analysis, root cause investigation, and documentation.