Senior Test Engineer, Hardware Compute Group

Amazon Amazon · Big Tech · TPE, Taiwan +1 · Hardware Development

Senior Test Engineer role focused on the development and testing of next-generation System-on-Chips (SOCs) for machine learning-enabled consumer products. Responsibilities include first silicon debug, defining test program flows, yield analysis, and supporting manufacturing test stages.

What you'd actually do

  1. First silicon debug with Design and OSAT Test Engineering.
  2. Defines test program flows and methods for solid test coverage.
  3. Drive final test yield analysis and corrective actions
  4. Finalize wafer-sort and final test programs in support of production
  5. Drive product to meet yield and test time/cost goals.

Skills

Required

  • Bachelor's degree in engineering, computer science or equivalent
  • Knowledge of the semiconductor industry, processes, technologies and key suppliers
  • 10+ years or more experience in semiconductor digital design, test and/or product engineering for complex SoC’s
  • Hands on experience & solid understanding of SOC development cycle in multiple ASIC projects
  • Hands on experience in successful new product introductions for multiple complex, high-volume SoCs in advanced process nodes
  • Strong knowledge of new product introduction from first silicon through product qualification and characterization
  • Good analytical, communication, team work, and troubleshooting and problem solving skills

Nice to have

  • Master's degree or Ph.D. degree in Electrical Engineering or related field
  • Good knowledge and debugging skill on ATE (J750 & Advantest 93K is preferred)
  • Chip design background in circuit/physical design (timing closure, power, etc.) or DV (correlating SW signatures to block level tests) is desirable
  • Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking, or yield improvements
  • Post silicon logic debug background in exercising various DFX features, analyzing scan-dump/mem-dump, suggesting tests in both system level and in DV
  • Product engineering background and familiarity with ATE coverage, margin, binning, scan pattern generation, etc
  • Knowledge of CPU, DDR4/LPDDR4/LPDDR5, USB, eMMC, CSI/DSI & MIPI characterization is a highly desired

What the JD emphasized

  • 10+ years or more experience in semiconductor digital design, test and/or product engineering for complex SoC’s
  • Must have hands on experience & solid understanding of SOC development cycle in multiple ASIC projects
  • Hands on experience in successful new product introductions for multiple complex, high-volume SoCs in advanced process nodes
  • Good knowledge and debugging skill on ATE (J750 & Advantest 93K is preferred)
  • Knowledge of CPU, DDR4/LPDDR4/LPDDR5, USB, eMMC, CSI/DSI & MIPI characterization is a highly desired