Senior Testchip Soc Physical Design Engineer (integration & Methodology)

Intel Intel · Semiconductors · Oregon, Hillsboro, United States +2

This role focuses on physical design and integration methodologies for testchip vehicles in advanced semiconductor process nodes, aiming to validate new technologies and ensure manufacturing readiness. It involves developing layout design, defining critical design features with process integration teams, establishing hierarchical layout specifications, and driving physical design convergence.

What you'd actually do

  1. Developing layout design methodology for testchip development in next generation process nodes
  2. Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
  3. Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
  4. Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
  5. Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools

Skills

Required

  • Master's degree in electrical engineering or related field with minimum of 5 years of experience
  • Experience with physical/layout design in advance technology nodes
  • In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
  • Design rules and layout constraints in advanced semiconductor processes
  • Experience with floorplanning, hierarchical design integration, and layout verification/debug

Nice to have

  • Experience in Definition of Testchip/Product design from Concept to Execution Commit
  • Experience in working with Foundry teams on negotiating features to exercise in design
  • Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
  • Previous related work experience in a semiconductor foundry

What the JD emphasized

  • physical/layout design in advance technology nodes
  • Design rules and layout constraints in advanced semiconductor processes