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We are now looking for a motivated Senior Timing Engineer (Circuits) to join our dynamic and growing Circuit Solutions Group! If you are a highly motivated individual who excels at improving design and timing quality and enjoys solving complex technical challenges through collaboration, we want to hear from you.
What you'll be doing:
- Participate in groundbreaking processor design in deep submicron technologies.
- Work as part of a global circuits team alongside circuit designers to drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).
- Apply knowledge and experience to standardize improving timing convergence flows while working with methodology teams.
- Develop timing models and methodology for innovative and unique custom macro designs.
- Validate timing of custom circuit designs using STA tools including PrimeTime, Tempus and various SPICE simulation tools.
- Work with circuit designers, tool developers, and timing methodology teams to validate macro level timing accuracy and correctness.
- Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation.
What we need to see:
- BS (or equivalent experience) in Electrical or Computer Engineering.
- 6+ years of experience for Masters and 8+ years for Bachelors with majority of experience in custom circuit timing analysis/signoff.
- Expertise and in-depth knowledge of industry standard STA tools such as Primetime, Tempus, and other timing analysis tools.
- Proven experience in timing constraints generation and management.
- Basic level understanding of transistor-level circuits and SPICE simulations for correlating to STA and noise results.
- Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise.
- Knowledge in process variation effect modeling and experience in design convergence in multi GHz deep submicron technology.
- Familiarity with clocking specs such as jitter, IR drop, skew, crosstalk, etc.
- Solid understanding of extracted timing models and the usage of .libs in Primetime.
- Great teammate with outstanding interpersonal skills.
Ways to stand out from the crowd:
- Understanding of DFT logic and experience with DFT timing signoff for various modes e.g., shift, capture, BIST, etc.
- Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs.
- Experience in critical path planning and crafting.
- Experience in methodology and/or flow development as well as automation.
- Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes as well as strong scripting skills for flow automation; experience with TCL, Python is a plus.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until March 21, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.