Senior Verification Engineer - Audio and Auxiliary Cpu Sub-systems

NVIDIA NVIDIA · Semiconductors · Bangalore, India +1

Senior Verification Engineer role focused on Audio and Auxiliary CPU Sub-Systems for automotive chips. Responsibilities include developing UVM-based verification test benches, defining test plans, building verification components, implementing functional coverage, and collaborating with cross-functional teams. Requires experience in verification closure of complex units/sub-systems/SOCs, RISCV/ARM/DSP core experience, and SV/UVM methodologies.

What you'd actually do

  1. You will develop UVM-based verification test benches and methodologies for unit level, write verification components and API's for cluster and system level test benches.
  2. Architect the testbenches and craft verification environment using SV, UVM and C/C++ methodology
  3. Define test plans, tests and verification infrastructure for clusters and systems
  4. Build efficient and reusable bus functional models, monitors, checkers, scoreboards, API's and encapsulated components
  5. Implement functional coverage and own unit, cluster and SOC level verification closure

Skills

Required

  • BTech or MTech in ECE, EE, CSE, or an equivalent degree
  • over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification
  • Proven experience in RISCV, ARM or DSP core based CPU sub-systems
  • Experience in the latest verification methodologies like SV and UVM
  • Good debugging and analytical skills
  • exposure to industry-standard verification tools for simulation and debug
  • Good interpersonal skills
  • ability to work as a diligent teammate
  • excellent communication skills

Nice to have

  • Exposure on using AI (like Claude and Cursor) extensively for code development
  • A mentality towards constant improvement and looking to build a multiplier effect through your work and automation
  • Exposure to Formal verification
  • An exposure to Audio functions, safety and reliability features and BOOT, power management features experience

What the JD emphasized

  • over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification