Senior Verification Engineer, Pcie

NVIDIA NVIDIA · Semiconductors · Bangalore, India

Senior Verification Engineer for PCI Express controllers, focusing on ASIC design verification using UVM and SystemVerilog. The role involves building verification components, understanding design specifications, and collaborating with cross-functional teams.

What you'd actually do

  1. Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  2. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  3. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  4. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Required

  • B.Tech./ M.Tech or equivalent experience
  • 5+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level
  • Expertise in Verilog and SystemVerilog
  • Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Background in DV methodologies like UVM/VMM
  • Exposure to industry standard verification tools for simulation and debug

Nice to have

  • Excellent knowledge of PCIE protocol - Gen3 and above
  • Good understanding of the system level architecture of PCIE/CXL-based designs
  • Perl, Python or similar scripting and SW programming language experience
  • Good debugging and analytical skills
  • Good interpersonal skills & dream to work as a great teammate

What the JD emphasized

  • 5+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
  • Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug