Senior Verification Engineer - Scalable Coherency Fabric

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

Seeking an experienced Senior Verification Engineer with expertise in interconnect/fabric and advanced verification methodologies for Nvidia's CPU team, focusing on the Scalable Coherency Fabric (SCF).

What you'd actually do

  1. As a member of the fabric verification team, you will be responsible for verifying the design, architecture and micro-architecture of Nvidia's scalable coherency fabric (SCF) using sophisticated verification methodologies
  2. You are encouraged to understand the design and it's implementation, define the verification scope, develop the testplan and coordinate tasks within the verification team
  3. Develop the verification infrastructure using innovative verification methodologies and formal verification techniques.
  4. Collaborate with architects, designers, pre- and post- silicon verification teams to accomplish your tasks.

Skills

Required

  • PhD, Master's Degree, Bachelor's Degree, or equivalent experience
  • 5+ years of relevant experience
  • Detailed knowledge of large-scale coherent interconnect architectures
  • Prior experience in verifying ARM AMBA (AXI/ACE/CHI) protocols or other high-performance interconnect protocols
  • Previous experience in Network-on-chip (NoC) build verification
  • Experience in building testbenches using System Verilog and UVM
  • Debugging and strong problem-solving abilities
  • Communication and interpersonal skills
  • Ability to operate within a dynamic and distributed team

Nice to have

  • A successful track record of mentoring junior engineers and interns is a huge plus
  • A strong background in computer architecture is helpful

What the JD emphasized

  • 5+ years of relevant experience
  • Detailed knowledge of large-scale coherent interconnect architectures
  • Prior experience in verifying ARM AMBA (AXI/ACE/CHI) protocols or other high-performance interconnect protocols
  • Previous experience in Network-on-chip (NoC) build verification
  • Experience in building testbenches using System Verilog and UVM