Serdes Rtl Design Engineer at AMD

What you'd actually do

Collaborate with architects to define micro-architecture for high-speed SerDes PHY.

Own RTL design for digital blocks such as calibration/adaptation loops, DSP, and CDR logic.

Apply low-power techniques and perform PPA (performance, power, area) trade-off analysis.

Develop block-level test benches and validate design functionality; support integration debug and static timing closure.

Run design checks using LINT, CDC, and RDC tools to ensure design quality.

Skills

Required

logic design concepts
RTL coding using Verilog/SystemVerilog
micro-architecture
design specifications
design checker tools
functional verification tools
synthesis flow
static timing analysis
low power design and methodology
design with multiple clock domains
mixed signal design
Python
Perl
TCL
scripting language
electrical engineering
computer engineering

Nice to have

SerDes PHY (PMA/PCS)
high-speed I/O protocol

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **

THE ROLE:

Join AMD’s SerDes Technology team to design and deliver high-performance, multi-protocol wireline transceivers in advanced CMOS processes. In this role, you will own RTL design for key digital components such as calibration loops, signal processing logic, and clock-data recovery. You will also contribute to micro-architecture planning, low-power design techniques, and performance, power, and area (PPA) optimization. This position involves close collaboration with system architects, analog designers, verification teams, and physical design engineers to achieve first-pass silicon success for AMD’s next-generation products.

THE PERSON:

You are a strategic and detail-oriented engineer who blends innovation with practical execution. You excel in front-end digital design and RTL development, thrive in solving complex technical challenges, and bring strong analytical and problem-solving skills to every project. You communicate with clarity, collaborate effectively across global teams, and adapt quickly to emerging technologies. You have the curiosity to continuously learn, the confidence to influence design decisions, and the drive to deliver high-quality silicon at scale.

KEY RESPONSIBILITIES:

Collaborate with architects to define micro-architecture for high-speed SerDes PHY.
Own RTL design for digital blocks such as calibration/adaptation loops, DSP, and CDR logic.
Apply low-power techniques and perform PPA (performance, power, area) trade-off analysis.
Develop block-level test benches and validate design functionality; support integration debug and static timing closure.
Run design checks using LINT, CDC, and RDC tools to ensure design quality.
Build behavioral models in Verilog/SystemVerilog to aid verification and system modeling.
Work closely with physical design and validation teams for tape-out sign-off and silicon bring-up.

PREFERRED EXPERIENCE:

Proficient in logic design concepts and RTL coding using Verilog/SystemVerilog
Proficient in micro-architecture and developing design specifications
Proficient with design checker tools and/or functional verification tools
Knowledge of synthesis flow and static timing analysis
Knowledge of low power design and methodology
Experience in design with multiple clock domains
Experience in mixed signal design
Experience with Python, Perl, TCL and/or other scripting language
Experience with SerDes PHY (PMA/PCS) and/or high-speed I/O protocol is preferred

**ACADEMIC CREDENTIALS: **

Bachelor's or master’s degree in electrical engineering, computer engineering, or related field

#LI-LC3

#LI-HYBRID

_Benefits offered are described: _AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

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This posting is for an existing vacancy.