Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Amazon Amazon · Big Tech · Austin, TX · Hardware Development

This role focuses on Signal and Power Integrity (SI/PI) analysis and optimization for advanced packaging solutions of machine learning and data center ASICs. The engineer will perform simulations, build models, and contribute to design decisions across IC, package, and board boundaries, working with senior engineers to meet performance and power delivery targets. Responsibilities include package-level SI/PI simulations, stack-up design support, high-speed channel simulations, modeling advanced interconnects, and validating decoupling technologies. The role also involves coordinating with SoC and board design teams and identifying potential manufacturing risks.

What you'd actually do

  1. Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers.
  2. Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
  3. Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance).
  4. Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths.
  5. Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors (DTCs), or IPD capacitors as needed.

Skills

Required

  • BS degree in electrical engineering or equivalent
  • 5+ years of experience in signal integrity, power integrity, or package design
  • Solid understanding of either SI (S-parameter extraction, crosstalk, return loss, channel analysis) or PI (PDN impedance analysis, IR drop, decoupling strategy), with working awareness of the other
  • Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent
  • Understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects
  • Familiarity with stack-up design and impedance control for multi-layer organic substrates or silicon interposers.
  • Good communication skills with the ability to participate in technical discussions across silicon, package, and board teams

Nice to have

  • MS with 3+ years in signal integrity, power integrity, or package design
  • Exposure to high-speed serial protocols (PCIe, UCIe, or custom SerDes) at the package level
  • Experience correlating SI/PI simulations with lab measurements (TDR, VNA, oscilloscope)
  • Familiarity with equalization techniques (DFE, CTLE, FFE) or PDN target impedance methodology
  • Interest or experience in package co-design methodologies (chip-package-board co-simulation)
  • Familiarity with high-density fan-out or silicon bridge packaging (e.g., EMIB, CoWoS, or similar)
  • Exposure to package-level thermal-aware analysis, electromigration, or EMC/EMI considerations

What the JD emphasized

  • advanced packaging solutions
  • machine learning
  • data center ASICs
  • package-level signal or power integrity
  • advanced packaging technologies
  • high-speed serial protocols