In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for next generation SoCs while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
- Participate in DFT logic insertion like scan and BIST at RTL and netlist level.
- Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
- Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support.
- Perform quality check flows like Lint, CDC, of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience in DFT specification and definition architecture and insertion.
- 2 years of experience with analog or mixed-signal IC design.
- Experience with DFT (Design for Test) technologies such as Scan, ATPG (Algorithmic Test Pattern Generation) and MBIST (Memory Built in Self Test.
- Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
Preferred qualifications:
- Master's degree in Electrical Engineering, or a related field.
- Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
- Experience in SoC cycles, including silicon bring-up and silicon debug activities.
- Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
- Experience in fault modeling.