Silicon Design Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

AMD is hiring a Silicon Design Engineer to research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing. The role involves ASIC development, including architecture design, logic design, system simulation, and evaluating the process flow from high-level designs to synthesis, place and route, and timing and power use. Responsibilities include developing synthesizable RTL (SystemVerilog/Verilog), implementing control logic, datapath, state machines, and protocol engines, ensuring RTL adherence to coding guidelines, supporting multi-clock domain designs, and designing/implementing PCIe/CXL protocol logic and system memory management.

What you'd actually do

  1. Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory.
  2. Perform definition, design, verification, and/or documentation for ASIC development.
  3. Determine architecture design, logic design, and/or system simulation.
  4. Evaluate all aspects of the process flow from high-level designs to synthesis, place and route, and timing and power use.
  5. Develops synthesizable RTL (SystemVerilog / Verilog) for complex digital blocks.

Skills

Required

  • Developing synthesizable RTL (SystemVerilog / Verilog) for complex digital blocks
  • Implementing control logic, datapaths, state machines, and protocol engines
  • Ensuring RTL adheres to coding guidelines, clocking/reset strategies, and low-power methodologies
  • Supporting multi-clock domain designs and CDC-safe implementations
  • Designing and implementing PCIe/CXL protocol related logic, including LTSSM, TLP/DLLP handling, credit management, error reporting, and compliance with PCIe Base Specification requirements
  • System memory management and CPU architecture

What the JD emphasized

  • Developing synthesizable RTL (SystemVerilog / Verilog) for complex digital blocks
  • Implementing control logic, datapaths, state machines, and protocol engines
  • Ensuring RTL adheres to coding guidelines, clocking/reset strategies, and low-power methodologies
  • Supporting multi-clock domain designs and CDC-safe implementations
  • Designing and implementing PCIe/CXL protocol related logic, including LTSSM, TLP/DLLP handling, credit management, error reporting, and compliance with PCIe Base Specification requirements
  • System memory management and CPU architecture