Silicon Design Engineering Leader

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Silicon Design Engineering Leader at AMD, focusing on driving SOC design execution, tape-outs, and people management. While the company is involved in AI and data centers, and may use AI for screening, the core responsibilities of this role are in traditional silicon design and engineering leadership, not direct AI/ML model development or deployment.

What you'd actually do

  1. Drive and lead SOC design execution with design team for all the design activities and successfully driving design to tape-outs.
  2. The candidate is also expected to take care of people management, performance management, employees career path, and match that to project needs.
  3. Work with management / leadership team for SOC planning, schedule, resource demand/supply, critical path analysis, and execution.
  4. Driving SOC design execution with local and global team.
  5. Driving team to deliver to SOC milestone and ensure all quality metrics are met on time.

Skills

Required

  • SOC planning
  • schedule
  • resource demand/supply
  • critical path analysis
  • execution
  • SOC design execution
  • SOC milestone delivery
  • quality metrics
  • architecture team collaboration
  • uArch definition
  • IP team collaboration
  • IP requirement
  • IP deliverables
  • negotiations
  • IP integration
  • Lint
  • CDC
  • RDC
  • Low-power implementation
  • VCLP
  • Equivalence Check
  • LEC
  • Formality
  • DV team collaboration
  • test plan review
  • coverage gap analysis
  • debug failures
  • PD team collaboration
  • Physical design feedback
  • ECOs implementation
  • execution meetings
  • scrums
  • standing meetings
  • bottleneck resolution
  • Project planning
  • deliverables
  • risk and mitigations options
  • status update presentation
  • contractor management
  • flex resource management
  • People management
  • appraisals
  • performance management
  • promotions
  • hiring talent
  • SOC integration
  • SOC fabrics
  • Voltage and clock domain crossings
  • Low power design
  • RTL Quality checks
  • Clock
  • Reset
  • Fuses
  • Synthesis
  • Timing Analysis
  • Design Partitioning
  • signoff
  • System bus understanding
  • IO protocol understanding
  • AXI
  • PCIe
  • Memory
  • System integration
  • multi-die methodology
  • system solution
  • managing execution team
  • project planning
  • IP delivery timelines
  • deliverables
  • quality checks
  • Resource planning
  • critical path analysis
  • risks
  • mitigation plan
  • VCS
  • SOC Connectivity
  • Spyglass Lint/CDC/RDC
  • SgLP
  • Synthesis – DC/FC

Nice to have

  • Perl
  • shell
  • Python
  • TCL

What the JD emphasized

  • ~15-25 years of strong experience in SOC