Silicon Design Verification Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for a Silicon Design Verification Engineer at AMD, focusing on validating the functional correctness of next-generation AMD/Xilinx programmable devices. The engineer will collaborate with architects and other engineers, define test plans, develop test benches using System Verilog and UVM, debug simulations, and review coverage metrics. Experience with computer architecture, logic design, System Verilog, UVM, and verification techniques is required, with preferred experience in C/C++, Assembly, scripting, gate-level simulation, power, and reset verification.

What you'd actually do

  1. Collaborate with architects, hardware and firmware engineers to understand the new features to be verified
  2. Take ownership of block level verification tasks
  3. Define test plans, test benches, and tests using System Verilog and UVM
  4. Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
  5. Review functional and code coverage metrics to meet the coverage requirements

Skills

Required

  • System Verilog
  • UVM
  • computer architecture
  • logic design
  • assertion verification
  • constraint-random verification
  • metric-driven verification

Nice to have

  • C/C++
  • Assembly programming languages
  • scripting (python preferred)
  • gate level simulation
  • power verification
  • reset verification

What the JD emphasized

  • Knowledge of Verilog, system Verilog and UVM is a must
  • Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification