Silicon Design Verification Engineer

AMD AMD · Semiconductors · Austin, TX · Engineering

This role is for a Silicon Design Verification Engineer at AMD. The engineer will be responsible for planning and executing verification of complex digital design blocks, creating testbenches, debugging tests, and performing coverage analysis. Experience with System Verilog, UVM, and simulation tools is preferred, along with an understanding of ASIC development phases and various verification techniques.

What you'd actually do

  1. Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  2. Interact with architects and design engineers to create a comprehensive verification test plan
  3. Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  4. Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  5. Debug tests with design engineers to deliver functionally correct design blocks
  6. Identify and write coverage measures for stimulus quality improvements
  7. Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Skills

Required

  • System Verilog
  • UVM

Nice to have

  • OVM
  • VMM
  • Verilog test benches
  • Synopsys VCS
  • Cadence IES
  • assertion-based verification
  • coverage-driven verification
  • ASIC development
  • full custom chip development
  • NOC (Network on Chip) verification
  • AXI3/4
  • DDR4/5
  • HBM
  • PCIe
  • Processors
  • Graphics
  • verification architect
  • FPGA verification
  • SOC verification
  • VLSI design
  • gate level simulation
  • power verification
  • reset verification
  • contention checking
  • abstraction techniques
  • verification management tools
  • regression management
  • Cadence (IEV)
  • Jasper
  • Synopsys (VC-Formal, Magellan)