Silicon Design Verification Engineer

AMD AMD · Semiconductors · San Jose, CA · Engineering

This role is for a Silicon Design Verification Engineer at AMD. The primary focus is on verifying complex digital design blocks for processors, FPGAs, and SOCs using System Verilog and UVM. The role involves planning verification, designing testbenches, debugging, and analyzing coverage. While the company mentions AI and next-generation computing, the core responsibilities of this specific role are in traditional hardware verification, not AI/ML model development or deployment.

What you'd actually do

  1. Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  2. Interact with architects and design engineers to create a comprehensive verification test plan
  3. Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  4. Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  5. Debug tests with design engineers to deliver functionally correct design blocks

Skills

Required

  • System Verilog
  • UVM
  • System Verilog Assertions (SVA)

Nice to have

  • OVM
  • VMM
  • Verilog test benches
  • Synopsys VCS
  • Cadence IES
  • block level NOC (Net work on Chip) verification
  • AXI3/4
  • DDR4/5
  • HBM
  • PCIe
  • Processors
  • Graphics
  • verification architect
  • gate level simulation
  • power verification
  • reset verification
  • contention checking
  • abstraction techniques
  • verification management tools
  • regression management
  • Cadence (IEV)
  • Jasper
  • Synopsys (VC-Formal, Magellan)