Silicon Design Verification Engineer (ai Debug/analysis)

AMD AMD · Semiconductors · Taipei, Taiwan · Engineering

This role is for a Silicon Design Verification Engineer at AMD, focusing on AI debug and analysis within the context of next-generation AMD SoCs. The responsibilities include understanding verification requirements, owning functional verification from planning to sign-off, and implementing testbenches using UVM methodology. While AI is mentioned in the context of debug and analysis, the core craft is silicon design verification, not building AI models or systems.

What you'd actually do

  1. Own or be involved in all aspects of the functional verification from initial test planning, test creation, and debug. to coverage and sign-off closure, while providing technical leadership to the team.
  2. Own verification of high-speed, low-power digital designs at the IP and System level using both coverage-driven constraints, random, and directed testing techniques, as well as formal verification.
  3. Implement test benches and components, such as test and sequence libraries, monitors, models, and BFMs, using object-oriented verification techniques aligned with the UVM methodology.

Skills

Required

  • Verilog
  • System Verilog
  • UVM methodology
  • ASIC Design flow
  • state of the art verification flow
  • power-aware simulation
  • firmware/hardware co-verification
  • AMBA (AXI, APB, AHB)
  • analytical and problem-solving skills
  • attention to detail
  • independently driving tasks

Nice to have

  • ACPI
  • GPIO
  • CLK
  • UART/DMA
  • SPI/eSPI
  • I2C/I3C
  • USB
  • PCIE

What the JD emphasized

  • AI debug/analysis experiences is a must
  • Strong AI coding and debugging experience