Silicon Design Verification Engineer Ll, Google Cloud

Google Google · Big Tech · Bengaluru, Karnataka, India

This role is for a Silicon Design Verification Engineer at Google Cloud, focusing on developing custom silicon solutions for Google's products. The engineer will be responsible for planning and executing verification of digital design blocks using SystemVerilog and UVM, creating verification environments, identifying coverage measures, debugging tests, and measuring coverage to ensure functional correctness and progress towards tape-out. The role is part of a team that supports AI and Infrastructure, including TPUs and Vertex AI.

What you'd actually do

  1. Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
  2. Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM).
  3. Identify and write all types of coverage measures for stimulus and corner-cases.
  4. Debug tests with design engineers to deliver functionally correct design blocks.
  5. Measure coverage to identify verification holes and to show progress towards tape-out.

Skills

Required

  • SystemVerilog
  • Universal Verification Methodology (UVM)
  • SystemVerilog Assertions (SVA)
  • functional coverage

Nice to have

  • Electrical Engineering
  • Computer Science
  • Computer Architecture
  • low-power design verification
  • verification testbenches
  • test cases
  • test environments
  • industry-standard simulators
  • revision control systems
  • regression systems
  • AI/ML accelerators
  • vector processing units

What the JD emphasized

  • Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 1 year of experience with verification methodology (e.g., Universal verification methodology (UVM)).
  • 1 year of experience in the verification of Internet Protocol (IP) designs (e.g., IP, SoC, vector CPUs).
  • Experience with SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage.