Silicon Design Verification Engineer, Tpu, Google Cloud

Google Google · Big Tech · Bengaluru, Karnataka, India

This role is for a Silicon Design Verification Engineer focused on digital design blocks and verification environments using SystemVerilog and UVM. The role involves planning verification, creating testbenches, identifying coverage, debugging, and measuring coverage to ensure functionally correct design blocks. While the team works on AI/ML accelerators and TPUs, the core function of this role is hardware verification, not direct AI/ML model development.

What you'd actually do

  1. Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
  2. Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM).
  3. Identify and write all types of coverage measures for stimulus and corner-cases.
  4. Debug tests with design engineers to deliver functionally correct design blocks.
  5. Measure coverage to identify verification holes and to show progress towards tape-out.

Skills

Required

  • Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 1 year of experience with verification methodology (e.g., Universal verification methodology (UVM)).
  • 1 year of experience in the verification of Internet Protocol (IP) designs (e.g., IP, SoC, vector CPUs).
  • Experience with SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage.

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
  • 2 years of experience with the full verification life cycle.
  • Experience in low-power design verification.
  • Experience developing and maintaining verification testbenches, test cases, and test environments.
  • Experience in artificial intelligence/machine learning (AI/ML) accelerators or vector processing units.
  • Experience with industry-standard simulators, revision control systems, and regression systems.

What the JD emphasized

  • verification methodology (e.g., Universal verification methodology (UVM))
  • verification of Internet Protocol (IP) designs (e.g., IP, SoC, vector CPUs)
  • SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage