Silicon Implementation Technologist

OpenAI OpenAI · AI Frontier · San Francisco, CA · Scaling

Seeking a senior Silicon Implementation Engineer to drive the construction and optimization of next-generation AI chips. This role involves hands-on work across architecture, circuits, memory, RTL, physical implementation, and integration, with a focus on PPA optimization and leveraging AI tools for engineering productivity. The goal is to translate ambitious product goals into manufacturable silicon for OpenAI's supercomputing infrastructure.

What you'd actually do

  1. Partner with architecture and system teams to translate product goals into executable silicon construction strategies.
  2. Drive hands-on optimization of power, performance, area, cost, and reliability across the silicon stack.
  3. Develop and implement solutions spanning circuits, memory, RTL, physical design, and integration.
  4. Use and build AI-driven tools, flows, and methodologies to accelerate silicon implementation.
  5. Evaluate new technologies and convert them into reliable product constructions optimized for performance, performance/TCO, and performance/W.

Skills

Required

  • BS with 12+ years, MS with 10+ years, or PhD with 6+ years of relevant industry experience in chip design or implementation.
  • Strong hands-on expertise in circuits and implementation-driven PPA optimization.
  • Deep knowledge of semiconductor technologies including memory, advanced nodes, packaging, and 3D integration.
  • Hands-on experience with RTL design and physical implementation through tapeout.
  • Proven ability to work across disciplines and solve complex technical problems end-to-end.
  • Strong use of AI tools for engineering productivity, analysis, coding, or design optimization.
  • Excellent technical communication and collaboration skills.

Nice to have

  • Strong first-principles understanding of AI chip architectures and training/inference workloads.
  • Experience improving silicon products through innovations in performance, power, cost, yield, or reliability.
  • Experience with HBM, SRAM, memory hierarchy design, or memory-centric optimization.
  • Experience building internal tools, models, or automation used by engineering teams.
  • Research lab experience and/or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

What the JD emphasized

  • hands-on optimization
  • AI-driven tools
  • hands-on expertise
  • Hands-on experience
  • solve complex technical problems end-to-end
  • Strong use of AI tools