Silicon Packaging Design Engineer

Intel Intel · Semiconductors · Penang, Malaysia

This role focuses on the physical layout design of Intel's silicon for packaging technology, involving optimization for performance, reliability, and manufacturability. It requires developing custom layouts, performing detailed planning and routing, verifying standard cell libraries, and executing layout verification processes. The engineer will use EDA tools, troubleshoot design issues, and collaborate with cross-functional teams to ensure seamless execution of silicon tape-in, driving innovative layout methodologies.

What you'd actually do

  1. Develop custom layouts for Intel's silicon used for its packaging technology.
  2. Perform detailed physical array planning, area optimization, and signal and power routings.
  3. Design and verify standard cell libraries, ensuring compliance with design rules, PDK specifications, and reliability requirements.
  4. Execute layout verification processes, including checks for electron migration, voltage drop (IR), self-heat, ESD, and other reliability metrics.
  5. Use custom auto-routers and placers to efficiently construct layouts and optimize designs.

Skills

Required

  • layout design
  • Cadence Virtuoso Layout Suite
  • EDA tools
  • analog device and metal layout fundamentals
  • design for manufacturing (DFM)
  • reliability verification processes
  • layout construction
  • debugging
  • full-chip top metal/analog routing design
  • tape-in assembly
  • route methodologies
  • performance verification for layout

Nice to have

  • solve complex technical problems
  • troubleshoot tool and methodology issues
  • floor planning tools and flows
  • library integration
  • design archiving processes
  • Effective communication skills
  • disciplined design processes