Silicon Packaging Design Engineer

Intel Intel · Semiconductors · Arizona, Phoenix, United States +1

Designs and implements physical layout and routing of silicon interposers and embedded bridges, collaborating with silicon, technology development, and hardware teams to optimize system-level design. Utilizes EDA tools for package layouts and analyzes design data to resolve checks for manufacturability.

What you'd actually do

  1. Design and implement physical layout and routing of silicon interposers and embedded bridges.
  2. Perform substrate fit and routing studies to evaluate design tradeoffs in performance, cost, and manufacturability.
  3. Collaborate closely with silicon, technology development and hardware teams to optimize system-level design, including silicon-package-board integration and pinout.
  4. Propose design updates changes for rules and conduct internal and external reviews to ensure design feasibility.
  5. Analyze design data and resolve design rule checks (DRCs) to achieve optimized and manufacturable package designs.

Skills

Required

  • Bachelor's degree with 3+ years of experience OR Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM related field
  • Proficiency in custom layout and Auto-place-and-route EDA tools including Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or Calibre.
  • Experience with silicon physical layout design and development, routing interconnects, and/or review tools.
  • 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals.
  • 1+ year of experience of Power Distribution and power integrity assessments.
  • 1+ year of experience of reliability requirements for interconnects.

Nice to have

  • Familiarity with industry-leading silicon physical design methodologies and workflows.
  • Ability to effectively collaborate across multi-disciplinary teams and communicate technical concepts clearly.
  • A passion for innovation, problem-solving, and continuous improvement in a fast-paced environment.
  • Prior experience in optimizing silicon performance and conducting tradeoff studies for advanced packaging designs.