Silicon Packaging Design Engineer

Intel Intel · Semiconductors · Arizona, Phoenix, United States

This role focuses on the physical design and layout of silicon packaging, including substrate design, routing, and optimization for performance, cost, and manufacturability. It involves collaboration with silicon and hardware teams and requires experience with specific package design tools and microelectronic package physical layout.

What you'd actually do

  1. Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
  2. Conduct substrate fit and routing studies to establish design, performance, and cost tradeoffs.
  3. Define and implement substrate design rules, conducting internal and external reviews to maintain quality standards.
  4. Analyze data, resolve Design Rule Checks (DRCs), and optimize designs for manufacturability and performance.
  5. Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.

Skills

Required

  • US Citizenship
  • Bachelor's degree in Electrical Engineering, Mechanical Engineering, or Material Sciences, with 0-1+ years of relevant experience, or related field.
  • Experience with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
  • Experience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversions.
  • Experience microelectronic package or PCB physical layout design and manufacturing processes.

Nice to have

  • Master Degree in Electrical Engineering, Mechanical Engineering, or Material Sciences or related field.
  • Experience in substrate design or I/O routing, or technology development.
  • Experience with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
  • Experience with scripting using Python, VB, C, or similar languages.