Soc Architect

AMD AMD · Semiconductors · Folsom, CA · Engineering

AMD is seeking a SoC Architect to join their AECG x86 Embedded Team. This role will focus on defining and driving cutting-edge SoC designs for embedded and commercial applications, working across silicon, firmware, and software. Responsibilities include leading SoC architecture, owning platform power and reset, defining SOC features, static timing analysis, high-speed I/O architecture, performance/power/reliability modeling, functional safety, and cross-functional leadership. The ideal candidate will have experience in X86, GPU, interconnect, HSIO, and Memory subsystems architecture, with a background in embedded markets and SOC design.

What you'd actually do

  1. Lead SoC architecture: define processor complex, interconnect/NoC, memory controllers/DRAM topology, IOMMU hierarchy, security islands, and subsystem boundaries; write clear architecture specifications and drive reviews to closure.
  2. Own platform power & reset intent: specify PWROK/PWROKRAW/reset/iso sequencing across rails and domains; ensure asynchronous PWROK de‑assertion behavior meets EGADS and safety requirements; partner with board/VR teams and FCH/ART owners.
  3. SOC Features ownership: Define and drive SOC features
  4. Static timing analysis definitions: work with IP, process and product teams to define STA strategies
  5. High‑speed I/O architecture: architect PCIe Gen5/Gen6 RC/EP topologies, NTB links, Ethernet MAC/PHY integration, clocking, lane bifurcation, and PHY interfaces; align controller programming models with NBIO/SYSHUB wrappers.

Skills

Required

  • SoC architecture
  • processor complex
  • interconnect/NoC
  • memory controllers/DRAM topology
  • IOMMU hierarchy
  • security islands
  • subsystem boundaries
  • architecture specifications
  • platform power & reset intent
  • PWROK/PWROKRAW/reset/iso sequencing
  • SOC Features
  • Static timing analysis
  • High‑speed I/O architecture
  • PCIe Gen5/Gen6 RC/EP topologies
  • NTB links
  • Ethernet MAC/PHY integration
  • clocking
  • lane bifurcation
  • PHY interfaces
  • controller programming models
  • NBIO/SYSHUB wrappers
  • Performance, power, and reliability modeling
  • CAC targets for GFX/NPU
  • guard‑bands/aging models
  • ARO/RO monitors
  • V/F/tj operating points
  • mission profiles
  • Functional safety (FuSa) & RAS
  • IP teams
  • Jama/PRS
  • external auditors and customer expectations
  • ISO‑26262 compliance
  • Cross‑functional leadership
  • program management
  • customer engineers
  • headline specs (CPU/GPU/NoC sizing, DRAM speed/width, PCIe/Ethernet/NTB)
  • schedules
  • deliverables
  • AMD vs. customer roles and responsibilities
  • Documentation & reviews
  • MAS/mPRS/PRS artifacts
  • reset/power specs
  • architectural confluence pages
  • HLD concept exits
  • LS[ABCD] milestones
  • X86
  • GPU
  • interconnect
  • HSIO
  • Memory subsystems architecture
  • RAS
  • Performance and Power bounding box definitions
  • BIOS/FW/SW/Systems
  • Embedded markets (automotive/networking/industrial)
  • SOC design and execution
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • X86
  • GPU
  • interconnect
  • HSIO
  • Memory subsystems architecture
  • RAS
  • Performance and Power bounding box definitions
  • Familiarity with BIOS/FW/SW/Systems
  • Embedded markets (automotive/networking/industrial)
  • SOC design and execution

What the JD emphasized

  • clear architecture specifications
  • guard‑bands/aging models
  • V/F/tj
  • allocate FuSa and RAS requirements
  • ISO‑26262 compliance