Soc Debug / Post-silicon Pnp Validation Engineer

Intel Intel · Semiconductors · California, Folsom, United States +2

Seeking a SoC Debug / Post-Silicon PnP Validation Engineer to perform power and performance validation, low-level debug, and complex analysis at the SoC level for Intel products. Responsibilities include developing DFD tools, automation scripts, root cause analysis, and collaborating with cross-functional teams.

What you'd actually do

  1. Execute comprehensive power and performance (PnP) validation for systems, subsystems, and SoC-level components, applying advanced problem-solving and analytical techniques
  2. Develop and implement innovative design for debug (DFD) tools, automation scripts, and validation strategies to optimize power and performance debug processes
  3. Conduct thorough root cause analysis to resolve complex triage failures, power marginality issues, and performance bottlenecks, ensuring product quality and reliability
  4. Collaborate effectively with cross-functional teams, including design engineers, validation teams, and high-volume manufacturing partners, to support SoC debug readiness and issue resolution
  5. Formulate comprehensive debug requirements and validation strategies for new product features at the system level, ensuring alignment with architectural and performance objectives

Skills

Required

  • SoC debug
  • validation platforms
  • Python
  • SoC design
  • architecture
  • microarchitecture fundamentals
  • Debugging tools
  • defect triaging
  • system-level root cause analysis

Nice to have

  • power management concepts
  • PPM
  • P-states
  • C-states
  • power measurement tools
  • NIDAQ-Intec
  • thermal control equipment
  • performance benchmarks
  • power-performance characterization methodologies