Job Details:
Job Description:
The job Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block.
As a **SoC Logic Design Engineer your responsibilities will include but are not limited to: **
- You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including:
- Creating a design to produce key assets that help improve product KPIs for discrete graphics products.
- Working with SoC Architecture and platform architecture teams to establish silicon requirements.
- Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.
- Creating micro architectural specification document for the design.
- Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.
- Driving vendor's methodology to meet world class silicon design standards.
- Architecting area and power efficient low latency designs with scalabilities and flexibilities.
- Power and Area efficient RTL logic design and DV support.
- Running tools to ensure lint-free and CDC/RDC clean design, VCLP.
- Synthesis and timing constraints.
The ideal candidate will exhibit the following behavioral traits:
- Ability to drive and improve digital design methodology to achieve high quality first silicon
- Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule
- Strong verbal and written communication skills
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
**Minimum qualifications: **
Bachelors degree in Electrical, Computer Engineering with 4+ Years relevant experience in the semiconductor industry.
OR Masters degree in Elecrtical, Computer Engineering with 3+ years relevant experience in the semiconductor industry
4+ years of experience in/with:
- Verilog and system verilog, synthesizeable RTL
- Modern design techniques and energy-efficient/low power logic design and power analysis
- Computer Architecture
- GPU
** Preferred qualifications**:
- Experience with FPGA emulation, silicon bring-up, characterization and debug
- Experience in multiple tape-outs reaching production with first pass silicon
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara
Business group:
As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.