Soc Dfx Staff Engineer

AMD AMD · Semiconductors · MARKHAM, Canada · Engineering

Seeking an experienced SoC DFX Engineer to define, design, and verify Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high-performance SoCs. This role involves collaboration with architecture, RTL, firmware, and verification teams to integrate DFX features for silicon validation, bring-up, and debug across the product lifecycle.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and firmware engineers to understand the new DFX features to be designed and verified.
  2. Work on designing and integrating DFX logic in complex SoCs.
  3. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  4. Estimate the time required to write the new feature tests and any required changes to the test environment
  5. Build the directed and random verification tests

Skills

Required

  • Verilog
  • SystemVerilog
  • SystemC
  • C++
  • UVM concepts
  • SystemVerilog language
  • static timing analysis and constraints

Nice to have

  • DFT (Design for Test) and DFD (Design for Debug) architecture, design, and verification
  • JTAG, LBIST, MBIST, Scan, and ATPG
  • Tessent tools suite, including Scan and ATPG
  • test pattern generation, bring-up, and debug on ATE
  • post-silicon bring-up
  • IP-level and ASIC verification
  • debugging firmware and RTL code using simulation tools
  • automating workflows in a distributed compute environment
  • Perl, Ruby, Makefile, and shell
  • leadership or mentorship

What the JD emphasized

  • complex SoCs
  • complex processor architectures
  • complex technical challenges