Soc Ip Methodology Engineer - Custom Soc

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +2

NVIDIA is seeking a Senior SOC/IP Methodology Engineer to design and architect next-generation custom SoC/IP solutions. The role involves developing and optimizing RTL to GDS methodologies, working with internal and external collaborators, and ensuring IP quality and integration. The engineer will be a hands-on domain expert in physical design, synthesis, timing, and layout, using EDA tools and scripting languages. Experience with high-performance designs like CPU, GPU, and machine learning IPs is required.

What you'd actually do

  1. Responsible for developing and optimizing semi-custom RTL to GDS methodologies, work with internal and external collaborators and IP Vendors on SOC/IP requirements and drive technology alignments across them.
  2. You will be a hands-on domain expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies and capabilities.
  3. Work with customers on SOC/IP development processes, IP quality and handoff requirements for QA, smooth integration, and high-quality analysis flows.
  4. You will drive, review, and cultivate development processes to assure top quality work to and from IP customers and SOC engineers.
  5. You will help in driving technical design reviews, assuring that defined processes are followed, identifying, and mitigating risks, and continuing to improve development processes with innovative tools and procedures.

Skills

Required

  • Masters with 8+ (or BS or equivalent experience with 10+) years of experience within these skill areas
  • Extensive leadership experience as Methodology and Technical expert in physical design working with internal and external partners
  • Experience working in a SOC development and customer focused environment with excellent interpersonal skills.
  • Experience in handling complex IP ecosystem involving both internal and external partners.
  • Proven hands-on experience with RTL-to-GDSII tool flows. physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk) etc.
  • Understanding of full flow (including DFT, BIST) to integrate customer and third-party IP and drive program alignment.
  • Proven abilities to optimize methodology and flows for high productivity, design optimization and incorporate innovation.
  • Strong background and knowledge in Synthesis, CTS, Power Optimization, Placement and Route methods and timing convergence for high performance designs like CPU, GPU and machine learning IPs.
  • Strong scripting skills involving Python, Perl and Tcl, excellent soft skills.

Nice to have

  • Exposure to IP-XACT or similar infrastructure is a plus.
  • RTL2GDS experience with high performance ARM cores, Serdes, DDR, GPU, machine learning experience would be a plus.

What the JD emphasized

  • Extensive leadership experience as Methodology and Technical expert in physical design working with internal and external partners
  • Proven hands-on experience with RTL-to-GDSII tool flows.
  • Strong background and knowledge in Synthesis, CTS, Power Optimization, Placement and Route methods and timing convergence for high performance designs like CPU, GPU and machine learning IPs.